1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for producing the memory device.
2. Description of the Related Art
In general, a MOS type semiconductor integrated circuit device is fabricated in such a way that a field oxide film is formed to isolate the device and that the source region and the drain region are formed by a self-aligning method using a gate electrode as a mask and implanting impurities into the substrate. The source region and the drain region have to be contacted together through one or two contacts for one transistor. This results in a disadvantage that the integration density is lowered depending on the contact margin of the regions and the wiring pitch thereof.
To cope with this problem, a semiconductor integrated circuit device having a planar cell structure is proposed (see Japanese Patent Application Laying Open (KOKAI) Nos .61-288464 and 63-96953).
In accordance with the planar cell structure, a continuous diffusion area as a common source region for a plurality of MOS transistors and a continuous diffusion area as a common drain region for a plurality of MOS transistors are formed on a substrate in parallel to each other. Also, on the substrate are formed gate electrodes which crossover both of the source and drain diffusion areas through an insulation film.
Due to the planar cell structure mentioned above, it becomes unnecessary to provide a field oxide film for device isolation and also it becomes possible to use one common contact for several or more transistors since each of the source diffusion area and the drain diffusion area is commonly used for a plurality of transistors, which makes it possible to achieve a high integration density of the device.
In accordance with a method for producing the planar cell structure memory device, the device is fabricated in such a way that, first, on a substrate are formed a field oxide film, diffusion areas for source and drain of the memory region, a gate oxide film and a gate electrode made from polycrystalline silicon (polysilicon). After that, a resist pattern having openings in a core portion (channel region) of the memory transistor is formed in accordance with the data to be written. After that, ions are implanted to raise the threshold voltage of the transistor so that the transistor is not turned on at a level of the value of the gate voltage for reading the data.
However, the above-mentioned planar cell structure has a disadvantage that the diffusion resistance becomes large since the bit line is elongated in the longitudinal diffusion region, which lowers the functional speed of the transistor.